ORTHO32

Problem

Predictable execution and explicit architectural state transitions.

Approach

SystemVerilog scalar pipeline, TLA+ specifications, Lean 4 developments, and a matrix-oriented instruction extension.

Verification and limits

FPGA and ASIC paths are under development. Published proofs concern their formal models; this site does not certify fabricated silicon or guarantee every AI workload completes in 768 cycles.

This project summary reviews public documentation. It does not substitute for the project's build, tests, proof audit, or independent evaluation.

License

BSL / AGPL / MPL — see terms. The actual project terms govern use.